Operand types, from Intel "Instruction Set Reference, A-M" section 3.1.1.2, Vol.
Enumerator |
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od_none |
Operand is not present as part of the instruction.
|
od_AL |
AL register.
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od_AX |
AX register.
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od_EAX |
EAX register.
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od_RAX |
RAX register.
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od_DX |
DX register.
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od_CS |
CS register.
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od_DS |
DS register.
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od_ES |
ES register.
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od_FS |
FS register.
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od_GS |
GS register.
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od_SS |
SS register.
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od_rel8 |
A relative address in the range from 128 bytes before the end of the instruction to 127 bytes after the end of the instruction.
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od_rel16 |
A relative address in the same code segment as the instruction assembled, with an operand size attribute of 16 bits.
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od_rel32 |
A relative address in the same code segment as the instruction assembled, with an operand size attribute of 32 bits.
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od_rel64 |
A relative address in the same code segment as the instruction assembled, with an operand size attribute of 64 bits.
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od_ptr16_16 |
A far pointer, typically to a code segment different from that of the instruction.
The notation 16:16 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16-bit selector or value destined for the code segment register. The value to the right corresponds to the offset within the destination segment. The ptr1616 symbol is used when the instruction's operand-size attribute is 16 bits.
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od_ptr16_32 |
A far pointer, typically to a code segment different from that of the instruction.
The notation 16:32 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16-bit selector or value destined for the code segment register. The value to the right corresponds to the offset within the destination segment. The ptr1632 symbol is used when the instruction's operand-size attribute is 32 bits.
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od_ptr16_64 |
A far pointer, typically to a code segment different from that of the instruction.
The notation 16:64 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16-bit selector or value destined for the code segment register. The value to the right corresponds to the offset within the destination segment. The ptr1664 symbol is used when the instruction's operand-size attribute is 64 bits.
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od_r8 |
One of the byte general-purpose registers: AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL; or one of the byte registers (R8L-R15L) available when using REX.R and 64-bit mode.
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od_r16 |
One of the word general-purpose registers: AX, CX, DX, BX, SP, BP, SI, DI; or one of the word registers (R8-R15) available when using REX.R and 64-bit mode.
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od_r32 |
One of the doubleword general-purpose registers: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; or one of the doubleword registers (R8D-R15D) available when using REX.R and 64-bit mode.
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od_r64 |
One of the quadword general-purpose registers: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8-R15.
These are available when using REX.R and 64-bit mode.
|
od_imm8 |
An immediate byte value, a signed number between -128 and +127, inclusive.
For instructions in which imm8 is combined with a word or doubleword operand, the immediate value is sign-extended to form a word or doubleword (the upper byte of the word is filled with the topmost bit of the immediate value).
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od_imm16 |
An immediate word value used for instructions whose operand-size attribute is 16 bits.
This is a number between -32,768 and +32,767 inclusive.
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od_imm32 |
An immediate doubleword value used for instructions whose operand-size attribute is 32 bits.
It allows the use of a number between -2,147,483,648 and +2,147,483,647 inclusive.
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od_imm64 |
An immediate quadword value used for instructions whose operand-size attribute is 64 bits.
The value allows the use of a number between -9,223,372,036,854,775,808 and +9,223,372,036,854,775,807 inclusive.
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od_r_m8 |
A byte operand that is either the contents of a byte general-purpose register (AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL) or a byte from memory.
Byte registers R8L-R15L are available using REX.R in 64-bit mode. This is indicated as "r/m8" in Intel documentation.
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od_r_m16 |
A word general-purpose register or memory operand used for instructions whose operand-size attribute is 16-bits.
The word general-purpose registers are AX, CX, DX, BX, SP, BP, SI, and DI. The contents of memory are found at the address provided by the effective address computation. Word registers R8W-R15W are available using REX.R in 64-bit mode. This is indicated as "r/m16" in Intel documentation.
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od_r_m32 |
A doubleword general-purpose register or memory operand used for instructions whose operand-size attribute is 32-bits.
The doubleword general-purpose registers are EAX, ECX, EDX, EBX, ESP, EBP, ESI, and EDI. The contents of memory are found at the address provided by the effective address computation. Doubleword registers R8D-R15D are available when using REX.R in 64-bit mode. This is indicated as "r/m32" in Intel documentation.
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od_r_m64 |
A quadword general-purpose register or memory operand used for instructions whose operand-size attribute is 64 bits when using REX.W.
Quadword general-purpose registers are RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8-R15; these are available only in 64-bit mode. The contents of memory are found at the address provided by the effective address computation. This is indicated as "r/m64" in Intel documentation.
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od_m |
A 16-, 32-, or 64-bit operand in memory.
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od_m8 |
A byte operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers.
In 64-bit mode, it is pointed to by the RSI or RDI registers.
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od_m16 |
A word operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers.
This nomenclature is used only with the string instructions.
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od_m32 |
A doubleword operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers.
This nomenclature is used only with the string instructions.
|
od_m64 |
A memory quadword operand in memory.
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od_m128 |
A memory double quadword operand in memory.
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od_m16_16 |
A memory operand containing a far pointer composed of two numbers.
In the notation 16:16, the number to the left of the colon corresponds to the pointer's segment selector while the number to the right corresponds to its offset.
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od_m16_32 |
A memory operand containing a far pointer composed of two numbers.
In the notation 16:16, the number to the left of the colon corresponds to the pointer's segment selector while the number to the right corresponds to its offset.
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od_m16_64 |
A memory operand containing a far pointer composed of two numbers.
In the notation 16:16, the number to the left of the colon corresponds to the pointer's segment selector while the number to the right corresponds to its offset.
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od_m16a16 |
A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the "a" (normally written "m16&16" in Intel manuals).
All memory addressing modes are allowed. This operand definition is used by the BOUND instruction to provide an operand containing an upper and lower bound for array indices.
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od_m16a32 |
A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the "a" (normally written "m16&32" in Intel manuals).
All memory addressing modes are allowed. This operand definition is used by the LIDT and LGDT to provide a word with which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and IDTR registers.
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od_m32a32 |
A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the "a" (normally written "m32&32" in Intel manuals).
All memory addressing modes are allowed. This operand definition is used by the BOUND instruction to provide an operand containing an upper and lower bound for array indices.
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od_m16a64 |
A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the "a" (normally written "m64&64" in Intel manuals).
All memory addressing modes are allowed. This operand definition is used by the LIDT and LGDT in 64-bit mode to provide a word with which to load the limit field, and a quadword with which to load the base field of the corresponding GDTR and IDTR registers.
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od_moffs8 |
A simple memory variable (memory offset) of type byte used by some variants of the MOV instruction.
The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. This is used by instructions with a 8-bit address size attribute.
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od_moffs16 |
A simple memory variable (memory offset) of type word used by some variants of the MOV instruction.
The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. This is used by instructions with a 16-bit address size attribute.
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od_moffs32 |
A simple memory variable (memory offset) of type doubleword used by some variants of the MOV instruction.
The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. This is used by instructions with a 32-bit address size attribute.
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od_moffs64 |
A simple memory variable (memory offset) of type quadword used by some variants of the MOV instruction.
The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. This is used by instructions with a 64-bit address size attribute.
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od_sreg |
A segment register.
The segment register bit assignments are ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5.
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od_m32fp |
A single-precision floating-point operand in memory used as operands for x87 FPU floating-point instructions.
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od_m64fp |
A double-precision floating-point operand in memory used as operands for x87 FPU floating-point instructions.
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od_m80fp |
A double extended-precision floating-point operand in memory used as operands for x87 FPU floating-point instructions.
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od_st0 |
The 0th (top) element of the FPU register stack.
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od_st1 |
The 1st (second-from-top) element of the FPU register stack.
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od_st2 |
The 2nd element of the FPU register stack.
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od_st3 |
The 3rd element of the FPU register stack.
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od_st4 |
The 4th element of the FPU register stack.
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od_st5 |
The 5th element of the FPU register stack.
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od_st6 |
The 6th element of the FPU register stack.
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od_st7 |
The 7th (bottom) element of the FPU register stack.
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od_sti |
Any element of the FPU register stack.
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od_mm |
An MMX register.
The 64-bit MMX registers are MM0 through MM7.
|
od_mm_m32 |
The low-order 32 bits of an MMX register or a 32-bit memory operand.
The contents of memory are found at the address provided by the effective address computation. This definition is called "mm/m32" in Intel documentation.
|
od_mm_m64 |
An MMX register or a 64-bit memory operand.
The contents of memory are found at the address provided by the effective address computation. This definition is called "mm/m64" in Intel documentation.
|
od_xmm |
An XMM register.
The 128-bit XMM registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode.
|
od_xmm_m16 |
See PMOVSXBQ.
|
od_xmm_m32 |
An XMM register or a 32-bit memory operand.
The 128-bit XMM registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.
|
od_xmm_m64 |
An XMM register or a 64-bit memory operand.
The 128-bit SIMD floating-point registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.
|
od_xmm_m128 |
An XMM register or a 128-bit memory operand.
The 128-bit SIMD floating-point registers are XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at the address provided by the effective address computation.
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od_XMM0 |
See BLENDVPD.
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od_0 |
See ENTER.
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od_1 |
See ENTER.
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od_m80 |
See FBLD.
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od_dec |
See FBLD.
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od_m80bcd |
See FBSTP.
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od_m2byte |
See FLDCW.
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od_m14_28byte |
See FLDENV.
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od_m94_108byte |
See FRSTOR.
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od_m512byte |
See FXRSTORE.
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od_r16_m16 |
See LAR.
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od_r32_m8 |
See PINSRB.
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od_r32_m16 |
See LAR.
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od_r64_m16 |
See SLDT.
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od_CR0 |
See MOV.
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od_CR7 |
See MOV.
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od_CR8 |
See MOV.
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od_CR0CR7 |
See MOV.
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od_DR0DR7 |
See MOV.
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od_reg |
See MOVMSKPD.
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od_CL |
See SAR.
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