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SgAsmPowerpcInstruction.C
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1 /* SgAsmPowerpcInstruction member definitions. Do not move them to src/ROSETTA/Grammar/BinaryInstruction.code (or any *.code
2  * file) because then they won't get indexed/formatted/etc. by C-aware tools. */
3 
4 #include "sage3basic.h"
5 #include "Disassembler.h"
6 
7 // Return control flow successors. See base class for full documentation.
8 Disassembler::AddressSet
9 SgAsmPowerpcInstruction::get_successors(bool *complete) {
10  Disassembler::AddressSet retval;
11  *complete = true; /*assume retval is the complete set of successors for now*/
12 
13  switch (get_kind()) {
14  case powerpc_bc:
15  case powerpc_bca:
16  case powerpc_bcl:
17  case powerpc_bcla: {
18  /* Conditional branches: bcX BO,BI,TARGET */
19  const std::vector<SgAsmExpression*> &exprs = get_operandList()->get_operands();
20  ROSE_ASSERT(exprs.size()==3);
21  ROSE_ASSERT(isSgAsmValueExpression(exprs[2]));
22  SgAsmValueExpression *ve = isSgAsmValueExpression(exprs[2]);
23  assert(ve!=NULL);
24  rose_addr_t target = SageInterface::getAsmConstant(ve);
25  retval.insert(target);
26  retval.insert(get_address()+get_size());
27  break;
28  }
29 
30  case powerpc_bcctr:
31  case powerpc_bcctrl:
32  case powerpc_bclr:
33  case powerpc_bclrl:
34  /* Conditional branches to count register; target is unknown */
35  *complete = false;
36  retval.insert(get_address()+get_size());
37  break;
38 
39  case powerpc_b:
40  case powerpc_ba:
41  case powerpc_bl:
42  case powerpc_bla: {
43  /* Unconditional branches */
44  const std::vector<SgAsmExpression*> &exprs = get_operandList()->get_operands();
45  ROSE_ASSERT(exprs.size()==1);
46  ROSE_ASSERT(isSgAsmValueExpression(exprs[0]));
47  SgAsmValueExpression *ve = isSgAsmValueExpression(exprs[0]);
48  assert(ve!=NULL);
49  rose_addr_t target = SageInterface::getAsmConstant(ve);
50  retval.insert(target);
51  break;
52  }
53 
54  case powerpc_unknown_instruction:
55  case powerpc_tw:
56  case powerpc_twi:
57  case powerpc_rfi:
58  case powerpc_sc:
59  /* No known successors */
60  *complete = false;
61  break;
62 
63  default:
64  /* All others fall through to next instruction */
65  retval.insert(get_address()+get_size());
66  break;
67  }
68  return retval;
69 }
70 
71 // Does instruction terminate basic block? See base class for full documentation.
72 bool
73 SgAsmPowerpcInstruction::terminates_basic_block() {
74  switch (get_kind()) {
75  case powerpc_unknown_instruction:
76  case powerpc_b: /* branch instructions... */
77  case powerpc_ba:
78  case powerpc_bl:
79  case powerpc_bla:
80  case powerpc_bc:
81  case powerpc_bca:
82  case powerpc_bcl:
83  case powerpc_bcla:
84  case powerpc_bcctr:
85  case powerpc_bcctrl:
86  case powerpc_bclr:
87  case powerpc_bclrl:
88  case powerpc_tw: /* trap instructions... */
89  case powerpc_twi:
90  case powerpc_sc: /* system call */
91  case powerpc_rfi: /* return from interrupt */
92  return true;
93 
94  default:
95  return false;
96  }
97 }
98 
99 // Determines whether this is the special PowerPC "unknown" instruction.
100 bool
101 SgAsmPowerpcInstruction::is_unknown() const
102 {
103  return powerpc_unknown_instruction == get_kind();
104 }
105