DisassemblerMips.h

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/* Disassembly specific to the MIPS architecture */
#ifndef ROSE_DISASSEMBLER_MIPS_H
#define ROSE_DISASSEMBLER_MIPS_H

#include "Disassembler.h"
#include "InstructionEnumsMips.h"
#include "sageBuilderAsm.h"

class DisassemblerMips: public Disassembler {
public:
    DisassemblerMips() { init(); }
    virtual DisassemblerMips *clone() const /*override*/ { return new DisassemblerMips(*this); }
    virtual bool can_disassemble(SgAsmGenericHeader*) const /*override*/;
    virtual SgAsmInstruction *disassembleOne(const MemoryMap*, rose_addr_t start_va, AddressSet *successors=NULL) /*override*/;
    virtual SgAsmInstruction *make_unknown_instruction(const Disassembler::Exception&) /*override*/;

    class Mips32 {
    public:
        enum Architecture { Release1, Release2, Release3, Micro };
        Mips32(Architecture arch, unsigned match, unsigned mask): arch(arch), match(match), mask(mask) {}
        virtual ~Mips32() {}
        Architecture arch;      // architecture where this instruction was introduced
        unsigned match;         // value of compared bits
        unsigned mask;          // bits of 'match' that will be compared
        typedef DisassemblerMips D;
        virtual SgAsmMipsInstruction *operator()(D *d, unsigned insn_bits) = 0;
    };

    Mips32 *find_idis(unsigned insn_bits);

    void insert_idis(Mips32*, bool replace=false);

    SgAsmMipsInstruction *disassemble_insn(unsigned insn_bits);


    // The following functions are used by the various instruction-specific Mips32 subclasses.

    rose_addr_t get_ip() const { return insn_va; }

    SgAsmMipsInstruction *makeInstruction(MipsInstructionKind, const std::string &mnemonic,
                                          SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL,
                                          SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL);

    SgAsmMipsRegisterReferenceExpression *makeRegister(unsigned regnum);

    SgAsmMipsRegisterReferenceExpression *makeFpRegister(unsigned regnum);

    SgAsmMipsRegisterReferenceExpression *makeCp0Register(unsigned regnum, unsigned sel);

    SgAsmMipsRegisterReferenceExpression *makeCp2Register(unsigned regnum);

    SgAsmMipsRegisterReferenceExpression *makeFpccRegister(unsigned cc);

    SgAsmMipsRegisterReferenceExpression *makeCp2ccRegister(unsigned cc);

    SgAsmMipsRegisterReferenceExpression *makeHwRegister(unsigned regnum);

    SgAsmMipsRegisterReferenceExpression *makeShadowRegister(unsigned regnum);

    SgAsmIntegerValueExpression *makeImmediate8(unsigned value, size_t bit_offset, size_t nbits);

    SgAsmIntegerValueExpression *makeImmediate16(unsigned value, size_t bit_offset, size_t nbits);

    SgAsmIntegerValueExpression *makeImmediate32(unsigned value, size_t bit_offset, size_t nbits);

    SgAsmIntegerValueExpression *makeBranchTargetRelative(unsigned offset16, size_t bit_offset, size_t nbits);

    SgAsmIntegerValueExpression *makeBranchTargetAbsolute(unsigned insn_index, size_t bit_offset, size_t nbits);

    SgAsmBinaryAdd *makeRegisterOffset(unsigned gprnum, unsigned offset16);

    SgAsmBinaryAdd *makeRegisterIndexed(unsigned base_gprnum, unsigned index_gprnum);

    SgAsmMemoryReferenceExpression *makeMemoryReference(SgAsmExpression *addr, SgAsmType *type);


protected:
    void init();

protected:
    std::vector<Mips32*> idis_table;

    rose_addr_t insn_va;
};

#endif